A Scalable FPGA Architecture for Real-Time Decoding of Quantum LDPC Codes
We present a scalable FPGA-based architecture for real-time decoding of quantum LDPC codes using the GARI decoding framework for correlated errors. Our approach combines message-passing decoding with resource-efficient hardware design techniques, including decoder-core reuse and controlled parallelism, enabling low-latency decoding while significantly reducing FPGA resource consumption. We implement the decoder on a Xilinx VCU19P FPGA targeting the [[144,12,12]] bivariate bicycle code, achieving sub-microsecond average decoding latency with improved hardware efficiency compared to previous implementations. These results highlight the potential of scalable and energy-efficient classical co-processors for future fault-tolerant quantum computing systems based on qLDPC codes.