Prakash Murali

Fault-tolerant quantum computing (FTQC) is a prerequisite for practical quantum advantage, yet a substantial gap separates today's hardware with physical error rates near 10⁻³ and hundreds of qubits from application requirements of sub-10⁻⁹ logical error rates and millions of qubits. Bridging this gap through quantum error correction incurs severe resource overheads, but these overheads are not fixed: they depend strongly on architectural organisation, error-correcting code choice, and compilation strategy. This talk argues that classical computer-architecture methodologies — design-space exploration, resource estimation, instruction-set and abstraction-boundary design, and hardware-aware compilation — are indispensable for navigating the transition to FTQC. Drawing on recent results across trapped-ion, superconducting, and distributed platforms, I show how architecture-level analysis localises the dominant scaling bottlenecks (wiring, power and thermal budgets, magic-state distillation, and inter-node communication) and how co-designing hardware, compilers, and error-correction schemes substantially reduces resource cost. I conclude by framing architectural pathfinding as a principled methodology for guiding hardware roadmaps.