Stefano Veroni

To reduce the large overhead of fully fault-tolerant (FT) universal computation, the framework of partial fault-tolerance has recently been proposed. While Clifford gates remain fully FT, arbitrary-angle rotations are natively implemented, rather than synthesised, at the expense of reduced resilience against specific protocol-dependent faults. While this "Space-Time efficient Analog Rotation" (STAR) architecture offers a potential orders-of-magnitude reduction in the cost of universal computation, its practicality depends on accurate noise modelling and hardware co-design. Our work rigorously characterises and further optimises the protocol’s performance, with a focus on neutral atom architectures. These are among the most promising platforms for digital computation, offering large scalability, high-fidelity operations, mid-circuit measurements, and non-local connectivity, as well as reduced error-correction overhead by means of ‘algorithmic’ fault-tolerance. We first improve the accuracy in the modelling of the protocol’s noise. Then we optimise physical gate implementations to address the scheme’s critical sensitivity to hardware faults. Finally, we assess its applicability and the required resources on a concrete task : time evolution of the Fermi-Hubbard model. Our results further validate the partially FT architecture for near term computation and open new prospects for its resilience and scalability.